Recently, there has been known a semiconductor memory device which uses a ferroelectric film as an insulating film for capacitors to make data storage nonvolatile.
Transition of the polarized state of a ferroelectric substance shows hysteresis characteristics, and remnant polarization exists in the ferroelectric substance even when a voltage applied to the ferroelectric substance becomes 0, and therefore, nonvolatile data storage is carried out utilizing the remnant polarization.
In order to read the nonvolatile data from the ferroelectric capacitors, it is necessary to apply voltage to the ferroelectric capacitors, and generally, reading is carried out by driving plate lines that constitute electrodes of the ferroelectric capacitors.
While the plate lines drive plural memory cells that are arranged in a word line direction, the capacitances of the ferroelectric capacitors that are driven by the plate lines are significantly larger than those of capacitors that are formed of a silicon oxide film, which are usually adopted in a dynamic semiconductor memory device, and therefore, load capacitances connected to the plate lines are excessively large. Further, since Ir or IrO is used as a material of the plate lines, the resistance of the plate lines is high.
The excessive load capacitances connected to the plate lines and the high resistance of the plate lines cause a problem that the access time of the memory device is significantly increased.
On the other hand, in order to drive the plate lines at an appropriate speed, MOS transistors of high driving abilities must be used, leading to increased power consumption and increased layout area.
So, as a method for resolving the excessive load capacitances of the plate lines and the increase in the layout area, there have been proposed circuit systems such as a plate line division system and a plate line voltage fixation system, and circuit operations.
Hereinafter, a description will be given of a conventional semiconductor memory device with a ferroelectric substance.
Initially, as for a first conventional system, assuming that the above-mentioned problems cannot be solved by the plate line driving system, there is disclosed a semiconductor circuit that is operated with voltage of plate lines being fixed, without driving the plate lines (for example, refer to Japanese Published Patent Application No. Hei.10-162587 (Patent Document 1)). According to this system, since the plate lines are not driven, the plate line driving time is omitted to prevent increase in the access time.
Further, as for a plate line division system that is a second conventional system, there is disclosed a semiconductor circuit in which plural plate lines are provided for one word line (for example, refer to Japanese Published Patent Application No. Hei.10-162589 (Patent Document 2)). According to this system, since plural plate lines are provided for one word line, only desired memory cells can be operated, thereby preventing increase in the load capacitances connected to the plate lines to prevent increase in the access time.
However, the above-mentioned conventional techniques may have the following drawbacks. Since a layout is not particularly designated in either Patent Document 1 or Patent Document 2, a generally conceivable layout is presumed.
Initially, in the system disclosed in Patent Document 1, usually a layout as shown in FIG. 11 is considered. Hereinafter, this layout will be described with reference to FIG. 11.
FIG. 11 is a plan view for explaining a semiconductor memory device according to the first conventional system. In the semiconductor memory device, there are disposed plural word lines WL extending in a column direction DWL, plural bit lines BL extending in a row direction DBL, one plate line CP as large as a memory array MA, sense amplifier circuits SA that are adjacent to the memory array MA in the row direction DBL of the memory array MA, and plate line voltage supply circuits CPD that are adjacent to the memory array MA in the column direction DWL of the memory array MA. The bit lines BL are connected to the sense amplifier circuits SA, and the plate line CP is connected to the plate line voltage supply circuits CPD.
This circuit system employs the operation mode with the voltage of the plate line CP being fixed, and usually, supply of voltage tote plate line is carried out at an end of the memory cell array MA. However, it has become obvious from an analysis by the inventors of the present invention that the following problem occurs when voltage is supplied to the plate line at only the periphery of the memory cell array. That is, when a specific memory cell is operated, since the resistance of the plate line is high in a non-operating memory cell disposed in the vicinity of the operating memory cell, the voltage of the plate line is likely to cause undershoot or overshoot temporarily and locally, leading to degradation in data holding of the memory cell.
For example, when a memory cell Pos1 shown in FIG. 11 is operated, the plate line voltage in the vicinity of the Pos1 varies, whereby the plate line voltage in the vicinity of the non-operating Pos2, which voltage is supplied from the periphery of the memory cell array, causes undersupply of voltage because the resistance of the plate line is high, and the plate line voltage in the vicinity of the Pos2 also varies with the variation in the plate line voltage in the vicinity of the Pos1, leading to simple writing operation of the memory cell in the vicinity of the Pos2, resulting in degradation of data holding of the memory cell.
Further, in order so solve the above-mentioned problem, when miniaturization of the memory cell array is considered, more plate line voltage generation circuits CPD must be provided, leading to increase in the area of the semiconductor memory device.
Especially, in the system disclosed in Patent Document 2, a layout as shown in FIG. 12 is usually considered.
Hereinafter, the layout will be described with reference to FIG. 12.
FIG. 12 is a plan view for explaining a semiconductor memory device according to the second conventional system. In the semiconductor memory device, there are disposed plate lines CP and word lines WL extending in the column direction DWL (two plate lines CP are disposed for one word line WL), bit lines BL extending in the row direction DBL, sense amplifier circuits SA that are adjacent to the memory array MA in the row direction DBL of the memory array MA, and plate line voltage supply circuits CPD that are adjacent to the memory array MA in the column direction DWL of the memory array MA. The bit lines BL are connected to the sense amplifier circuits SA, and the plate lines CP are connected to the plate line voltage supply circuits CPD.
In this system, when miniaturization and high-density integration of the semiconductor memory device with a ferroelectric substance are proceeded, the load capacitance and resistance of the plate lines CP reach non-negligible levels, resulting in obstacles in promoting further speed-up.
Further, in order to solve the above-mentioned problem, when increase in the capability of driving the plate lines CP is considered, transistors of large driving capabilities must be used for the plate line voltage generation circuits CPD, leading to increase in the area of the plate line voltage generation circuits CPD.
Further, when further division of the plate lines CP is considered to solve the above-mentioned problem, more plate line voltage generation circuits CPD must be provided, leading to increase in the area of the ferroelectric substance memory device.